armOS
0.1.0
Minimal ARM Operating System for the Raspberry Pi - Documentation generated for Pi 4.
gpio.h
Go to the documentation of this file.
1
8
#ifndef P_GPIO_H
9
#define P_GPIO_H
10
11
#include <
peripherals/base.h
>
12
17
typedef
enum
{
18
GF_INPUT
= 0,
19
GF_OUTPUT
= 1,
20
GF_ALT_0
= 4,
21
GF_ALT_1
= 5,
22
GF_ALT_2
= 6,
23
GF_ALT_3
= 7,
24
GF_ALT_4
= 3,
25
GF_ALT_5
= 2,
26
}
gpio_func
;
27
32
enum
33
{
39
GPIO_BASE
= (
MMIO_BASE
+ 0x200000),
40
45
GPFSEL0
= (
GPIO_BASE
+ 0x00),
46
GPFSEL1
= (
GPIO_BASE
+ 0x04),
47
GPFSEL2
= (
GPIO_BASE
+ 0x08),
48
GPFSEL3
= (
GPIO_BASE
+ 0x0C),
49
GPFSEL4
= (
GPIO_BASE
+ 0x10),
50
GPFSEL5
= (
GPIO_BASE
+ 0x14),
55
GPSET0
= (
GPIO_BASE
+ 0x1C),
56
GPSET1
= (
GPIO_BASE
+ 0x20),
61
GPCLR0
= (
GPIO_BASE
+ 0x28),
62
GPCLR1
= (
GPIO_BASE
+ 0x2C),
64
GPLEV0
= (
GPIO_BASE
+ 0x34),
65
GPLEV1
= (
GPIO_BASE
+ 0x38),
66
GPEDS0
= (
GPIO_BASE
+ 0x40),
67
GPEDS1
= (
GPIO_BASE
+ 0x44),
68
GPREN0
= (
GPIO_BASE
+ 0x4C),
69
GPREN1
= (
GPIO_BASE
+ 0x50),
70
GPFEN0
= (
GPIO_BASE
+ 0x58),
71
GPFEN1
= (
GPIO_BASE
+ 0x5C),
72
GPHEN0
= (
GPIO_BASE
+ 0x64),
73
GPHEN1
= (
GPIO_BASE
+ 0x68),
74
GPLEN0
= (
GPIO_BASE
+ 0x70),
75
GPLEN1
= (
GPIO_BASE
+ 0x74),
76
GPAREN0
= (
GPIO_BASE
+ 0x7C),
77
GPAREN1
= (
GPIO_BASE
+ 0x80),
78
GPAFEN0
= (
GPIO_BASE
+ 0x88),
79
GPAFEN1
= (
GPIO_BASE
+ 0x8C),
81
#
if
defined(MODEL_0) || defined(MODEL_2) || defined(MODEL_3)
82
/* Broadcom 2835, 2836, 2837 specific GPIO registers */
87
GPPUD = (
GPIO_BASE
+ 0x94),
88
/*
89
* GPIO Pin Pull-up/down Enable Clocks 0,1
90
* Controls actuation of pull up/down for specific GPIO pins
91
*/
92
GPPUDCLK0 = (
GPIO_BASE
+ 0x98),
93
GPPUDCLK1 = (
GPIO_BASE
+ 0x9C)
95
#elif defined(MODEL_4)
96
/* Broadcom 2711 specific GPIO registers */
97
/*
98
* GPIO Pull-up / Pull-down Registers 0,1,2,3
99
* Controls the actuation of the internal pull-up/down resistors.
100
* Reading these registers gives the current pull-state.
101
*/
102
GPIO_PUP_PDN_CNTRL_REG0
= (
GPIO_BASE
+ 0xE4),
103
GPIO_PUP_PDN_CNTRL_REG1
= (
GPIO_BASE
+ 0xE8),
104
GPIO_PUP_PDN_CNTRL_REG2
= (
GPIO_BASE
+ 0xEC),
105
GPIO_PUP_PDN_CNTRL_REG3
= (
GPIO_BASE
+ 0xF0)
106
#endif
107
};
108
109
#endif
GPIO_BASE
@ GPIO_BASE
Definition:
gpio.h:39
GPAFEN1
@ GPAFEN1
Definition:
gpio.h:79
GPEDS0
@ GPEDS0
Definition:
gpio.h:66
GPCLR1
@ GPCLR1
Definition:
gpio.h:62
GPFSEL1
@ GPFSEL1
Definition:
gpio.h:46
GF_ALT_1
@ GF_ALT_1
Definition:
gpio.h:21
GF_INPUT
@ GF_INPUT
Definition:
gpio.h:18
GPIO_PUP_PDN_CNTRL_REG1
@ GPIO_PUP_PDN_CNTRL_REG1
Definition:
gpio.h:103
GPLEV1
@ GPLEV1
Definition:
gpio.h:65
GPREN1
@ GPREN1
Definition:
gpio.h:69
GPIO_PUP_PDN_CNTRL_REG3
@ GPIO_PUP_PDN_CNTRL_REG3
Definition:
gpio.h:105
GPAFEN0
@ GPAFEN0
Definition:
gpio.h:78
base.h
Definition of base MMIO registers addresses.
GPIO_PUP_PDN_CNTRL_REG2
@ GPIO_PUP_PDN_CNTRL_REG2
Definition:
gpio.h:104
GPEDS1
@ GPEDS1
Definition:
gpio.h:67
GPFSEL3
@ GPFSEL3
Definition:
gpio.h:48
GPAREN0
@ GPAREN0
Definition:
gpio.h:76
GPHEN0
@ GPHEN0
Definition:
gpio.h:72
GPFSEL5
@ GPFSEL5
Definition:
gpio.h:50
GPAREN1
@ GPAREN1
Definition:
gpio.h:77
GF_ALT_5
@ GF_ALT_5
Definition:
gpio.h:25
GPFSEL0
@ GPFSEL0
Definition:
gpio.h:45
GF_ALT_3
@ GF_ALT_3
Definition:
gpio.h:23
GF_ALT_0
@ GF_ALT_0
Definition:
gpio.h:20
GF_OUTPUT
@ GF_OUTPUT
Definition:
gpio.h:19
GPFEN1
@ GPFEN1
Definition:
gpio.h:71
GPFSEL4
@ GPFSEL4
Definition:
gpio.h:49
GPLEV0
@ GPLEV0
Definition:
gpio.h:64
GPIO_PUP_PDN_CNTRL_REG0
@ GPIO_PUP_PDN_CNTRL_REG0
Definition:
gpio.h:102
GPSET1
@ GPSET1
Definition:
gpio.h:56
GPFSEL2
@ GPFSEL2
Definition:
gpio.h:47
GPCLR0
@ GPCLR0
Definition:
gpio.h:61
GPREN0
@ GPREN0
Definition:
gpio.h:68
GPHEN1
@ GPHEN1
Definition:
gpio.h:73
GPSET0
@ GPSET0
Definition:
gpio.h:55
gpio_func
gpio_func
Definition:
gpio.h:17
MMIO_BASE
@ MMIO_BASE
Definition:
base.h:29
GF_ALT_4
@ GF_ALT_4
Definition:
gpio.h:24
GPLEN0
@ GPLEN0
Definition:
gpio.h:74
GPFEN0
@ GPFEN0
Definition:
gpio.h:70
GPLEN1
@ GPLEN1
Definition:
gpio.h:75
GF_ALT_2
@ GF_ALT_2
Definition:
gpio.h:22
include
peripherals
gpio.h
Generated by
1.8.17