peripherals

Raspberry Pi Peripherals addresses. More...

Files
file	aux.h
	Definition of AUX registers addresses (Only for Uart).
file	base.h
	Definition of base MMIO registers addresses.
file	gpio.h
	Definition of GPIO registers addresses.
file	irq.h
	Definition of IRQ registers addresses.
file	mbox.h
	Definition of Mailbox registers addresses.
file	timer.h
	Definition of System Timer registers addresses.

Macros
#define	TIMER_CLK_HZ   1000000
#define	TIMER_CLK_1000_HZ   1000

Enumerations
enum	{   AUX_BASE = (GPIO_BASE + 0x15000),   AUX_ENABLES = (AUX_BASE + 0x04),   AUX_MU_IO_REG = (AUX_BASE + 0x40),   AUX_MU_IER_REG = (AUX_BASE + 0x44),   AUX_MU_IIR_REG = (AUX_BASE + 0x48),   AUX_MU_LCR_REG = (AUX_BASE + 0x4C),   AUX_MU_MCR_REG = (AUX_BASE + 0x50),   AUX_MU_LSR_REG = (AUX_BASE + 0x54),   AUX_MU_MSR_REG = (AUX_BASE + 0x58),   AUX_MU_SCRATCH = (AUX_BASE + 0x5C),   AUX_MU_CNTL_REG = (AUX_BASE + 0x60),   AUX_MU_STAT_REG = (AUX_BASE + 0x64),   AUX_MU_BAUD_REG = (AUX_BASE + 0x68) }
enum	{ MMIO_BASE = 0xFE000000 }
enum	gpio_func {   GF_INPUT = 0,   GF_OUTPUT = 1,   GF_ALT_0 = 4,   GF_ALT_1 = 5,   GF_ALT_2 = 6,   GF_ALT_3 = 7,   GF_ALT_4 = 3,   GF_ALT_5 = 2 }
enum	{   GPIO_BASE = (MMIO_BASE + 0x200000),   GPFSEL0 = (GPIO_BASE + 0x00),   GPFSEL1 = (GPIO_BASE + 0x04),   GPFSEL2 = (GPIO_BASE + 0x08),   GPFSEL3 = (GPIO_BASE + 0x0C),   GPFSEL4 = (GPIO_BASE + 0x10),   GPFSEL5 = (GPIO_BASE + 0x14),   GPSET0 = (GPIO_BASE + 0x1C),   GPSET1 = (GPIO_BASE + 0x20),   GPCLR0 = (GPIO_BASE + 0x28),   GPCLR1 = (GPIO_BASE + 0x2C),   GPLEV0 = (GPIO_BASE + 0x34),   GPLEV1 = (GPIO_BASE + 0x38),   GPEDS0 = (GPIO_BASE + 0x40),   GPEDS1 = (GPIO_BASE + 0x44),   GPREN0 = (GPIO_BASE + 0x4C),   GPREN1 = (GPIO_BASE + 0x50),   GPFEN0 = (GPIO_BASE + 0x58),   GPFEN1 = (GPIO_BASE + 0x5C),   GPHEN0 = (GPIO_BASE + 0x64),   GPHEN1 = (GPIO_BASE + 0x68),   GPLEN0 = (GPIO_BASE + 0x70),   GPLEN1 = (GPIO_BASE + 0x74),   GPAREN0 = (GPIO_BASE + 0x7C),   GPAREN1 = (GPIO_BASE + 0x80),   GPAFEN0 = (GPIO_BASE + 0x88),   GPAFEN1 = (GPIO_BASE + 0x8C),   GPIO_PUP_PDN_CNTRL_REG0 = (GPIO_BASE + 0xE4),   GPIO_PUP_PDN_CNTRL_REG1 = (GPIO_BASE + 0xE8),   GPIO_PUP_PDN_CNTRL_REG2 = (GPIO_BASE + 0xEC),   GPIO_PUP_PDN_CNTRL_REG3 = (GPIO_BASE + 0xF0) }
enum	{   IRQ_BASE = (MMIO_BASE + 0xB000),   IRQ0_PENDING_0 = (IRQ_BASE + 0x200),   IRQ0_PENDING_1 = (IRQ_BASE + 0x204),   IRQ0_PENDING_2 = (IRQ_BASE + 0x208),   IRQ0_SET_EN_0 = (IRQ_BASE + 0x210),   IRQ0_SET_EN_1 = (IRQ_BASE + 0x214),   IRQ0_SET_EN_2 = (IRQ_BASE + 0x218),   IRQ0_CLR_EN_0 = (IRQ_BASE + 0x220),   IRQ0_CLR_EN_1 = (IRQ_BASE + 0x224),   IRQ0_CLR_EN_2 = (IRQ_BASE + 0x228),   AUX_IRQ = (1 << 29),   SYSTEM_TIMER_IRQ_0 = (1 << 0),   SYSTEM_TIMER_IRQ_1 = (1 << 1),   SYSTEM_TIMER_IRQ_2 = (1 << 2),   SYSTEM_TIMER_IRQ_3 = (1 << 3) }
enum	{   MBOX_BASE = (MMIO_BASE + 0xB880),   MBOX_READ = (MBOX_BASE + 0x00),   MBOX_STATUS = (MBOX_BASE + 0x18),   MBOX_WRITE = (MBOX_BASE + 0x20) }
enum	{   TIMER_BASE = (MMIO_BASE + 0x3000),   TIMER_CS = (TIMER_BASE + 0x00),   TIMER_CLO = (TIMER_BASE + 0x04),   TIMER_CHI = (TIMER_BASE + 0x08),   TIMER_C0 = (TIMER_BASE + 0x0c),   TIMER_C1 = (TIMER_BASE + 0x10),   TIMER_C2 = (TIMER_BASE + 0x14),   TIMER_C3 = (TIMER_BASE + 0x18),   TIMER_CS_M0 = (1 << 0),   TIMER_CS_M1 = (1 << 1),   TIMER_CS_M2 = (1 << 2),   TIMER_CS_M3 = (1 << 3) }

Detailed Description

Raspberry Pi Peripherals addresses.

Macro Definition Documentation

TIMER_CLK_1000_HZ

#define TIMER_CLK_1000_HZ   1000

System's Timer Clock Frequency / 1000 (for delays in msec).

TIMER_CLK_HZ

#define TIMER_CLK_HZ   1000000

System's Timer Clock Frequency (for delays in sec).

Enumeration Type Documentation

anonymous enum

anonymous enum

AUX registers addresses.

Enumerator
AUX_BASE	The base address for UART. For raspi 0,1: AUX_BASE = 0x20215000; For raspi 4: AUX_BASE = 0xFE215000;
AUX_ENABLES	Auxiliary Enables
AUX_MU_IO_REG	Mini UART I/O Data
AUX_MU_IER_REG	Mini UART Interrupt Enable
AUX_MU_IIR_REG	Mini UART Interrupt Identify
AUX_MU_LCR_REG	Mini UART Line Control
AUX_MU_MCR_REG	Mini UART Model Control
AUX_MU_LSR_REG	Mini UART Line Status
AUX_MU_MSR_REG	Mini UART Modem Status
AUX_MU_SCRATCH	Mini UART Scratch
AUX_MU_CNTL_REG	Mini UART Extra Control
AUX_MU_STAT_REG	Mini UART Extra Status
AUX_MU_BAUD_REG	Mini UART Baudrate

anonymous enum

anonymous enum

The MMIO area base address

Enumerator
MMIO_BASE	For raspi 4: MMIO_BASE = 0xFE000000

anonymous enum

anonymous enum

GPIO registers addresses.

Enumerator
GPIO_BASE	The base address for GPIO. For raspi 0,1: GPIO_BASE = 0x20200000; For raspi 4: GPIO_BASE = 0xFE200000;
GPFSEL0	GPIO Function Select 0,1,2,3,4,5 GPFSELn register are used to control alternative functions for pins: GPFSEL0: pins 0-9
GPFSEL1	GPFSEL1: pins 10-19
GPFSEL2	GPFSEL2: pins 20-29
GPFSEL3	GPFSEL3: pins 30-39
GPFSEL4	GPFSEL4: pins 40-49
GPFSEL5	GPFSEL5: pins 50-53 or 50-57
GPSET0	GPIO Pin Output Set 0,1 The GPSET0 register is used to set GPIO pins 0-31
GPSET1	The GPSET1 register is used to set GPIO pins 32-53
GPCLR0	GPIO Pin Output Clear 0,1 The GPCLR0 register is used to clear GPIO pins 0-31
GPCLR1	The GPCLR1 register is used to clear GPIO pins 32-53
GPLEV0	GPIO Pin Level 0
GPLEV1	GPIO Pin Level 1
GPEDS0	GPIO Pin Event Detect Status 0
GPEDS1	GPIO Pin Event Detect Status 1
GPREN0	GPIO Pin Rising Edge Detect Enable 0
GPREN1	GPIO Pin Rising Edge Detect Enable 1
GPFEN0	GPIO Pin Falling Edge Detect Enable 0
GPFEN1	GPIO Pin Falling Edge Detect Enable 1
GPHEN0	GPIO Pin High Detect Enable 0
GPHEN1	GPIO Pin High Detect Enable 1
GPLEN0	GPIO Pin Low Detect Enable 0
GPLEN1	GPIO Pin Low Detect Enable 1
GPAREN0	GPIO Pin Async. Rising Edge Detect 0
GPAREN1	GPIO Pin Async. Rising Edge Detect 1
GPAFEN0	GPIO Pin Async. Falling Edge Detect 0
GPAFEN1	GPIO Pin Async. Falling Edge Detect 1
GPIO_PUP_PDN_CNTRL_REG0	GPIO Pull-up / Pull-down Registers 0
GPIO_PUP_PDN_CNTRL_REG1	GPIO Pull-up / Pull-down Registers 1
GPIO_PUP_PDN_CNTRL_REG2	GPIO Pull-up / Pull-down Registers 2
GPIO_PUP_PDN_CNTRL_REG3	GPIO Pull-up / Pull-down Registers 3

anonymous enum

anonymous enum

The base address for IRQ

Enumerator
IRQ_BASE	The base address for IRQ. For raspi 0,1: IRQ_BASE = 0x2000B000; For raspi 4: IRQ_BASE = 0xFE00B000;
IRQ0_PENDING_0	ARM Core 0 IRQ Enabled Interrupt Pending bits [31:0]
IRQ0_PENDING_1	ARM Core 0 IRQ Enabled Interrupt pending bits [63:32]
IRQ0_PENDING_2	ARM Core 0 IRQ Enabled Interrupt pending bits [79:64]
IRQ0_SET_EN_0	Write to Set ARM Core 0 IRQ enable bits [31:0]
IRQ0_SET_EN_1	Write to Set ARM Core 0 IRQ enable bits [63:32]
IRQ0_SET_EN_2	Write to Set ARM Core 0 IRQ enable bits[79:64]
IRQ0_CLR_EN_0	Write to Clear ARM Core 0 IRQ enable bits [31:0]
IRQ0_CLR_EN_1	Write to Clear ARM Core 0 IRQ enable bits [63:32]
IRQ0_CLR_EN_2	Write to Clear ARM Core 0 IRQ enable bits [79:64]
AUX_IRQ	The AUX bit for enabling/disabling AUX interrupts
SYSTEM_TIMER_IRQ_0	The System Timer 0 bit for enabling/disabling timer interrupts
SYSTEM_TIMER_IRQ_1	The System Timer 1 bit for enabling/disabling timer interrupts
SYSTEM_TIMER_IRQ_2	The System Timer 2 bit for enabling/disabling timer interrupts
SYSTEM_TIMER_IRQ_3	The System Timer 3 bit for enabling/disabling timer interrupts

anonymous enum

anonymous enum

The offsets for Mailbox registers (For raspi 3,4).

Enumerator
MBOX_BASE	The base address for Mailbox registers
MBOX_READ	Reads messages from the GPU
MBOX_STATUS	Status for READ and WRITE registers
MBOX_WRITE	Writes messages to the GPU

anonymous enum

anonymous enum

System Timer registers

Enumerator
TIMER_BASE	The base address for System Timers. For raspi 0,1: TIMER_BASE = 0x20003000; For raspi 4: TIMER_BASE = 0xFE003000;
TIMER_CS	System Timer Control/Status
TIMER_CLO	System Timer Counter Lower 32 bits
TIMER_CHI	System Timer Counter Higher 32 bits
TIMER_C0	System Timer Compare 0
TIMER_C1	System Timer Compare 1
TIMER_C2	System Timer Compare 2
TIMER_C3	System Timer Compare 3
TIMER_CS_M0	System Timer Match 0
TIMER_CS_M1	System Timer Match 1
TIMER_CS_M2	System Timer Match 2
TIMER_CS_M3	System Timer Match 3

gpio_func

enum gpio_func

GPIO Pins available functionalities: 5 Alternative Functions, Input, Output.

Enumerator
GF_INPUT	Input
GF_OUTPUT	Output
GF_ALT_0	Alternative Function 0
GF_ALT_1	Alternative Function 1
GF_ALT_2	Alternative Function 2
GF_ALT_3	Alternative Function 3
GF_ALT_4	Alternative Function 4
GF_ALT_5	Alternative Function 5