entry

Exception type values - System Registers - ARMv8-a. More...

Files
file	entry.h
	Definition of armv8-a Invalid exception type values.
file	sysregs.h
	Definition of armv8-a system registers.
file	utils.h
	Definition of basic ARM assembly functions.

Functions
int	get_el ()

Registers
Size of all saved registers (31 8-byte registes)
#define	S_FRAME_SIZE   256

EL1t
For exceptions taken from EL1 while stack pointer was shared with EL0
#define	SYNC_INVALID_EL1t   0
#define	IRQ_INVALID_EL1t   1
#define	FIQ_INVALID_EL1t   2
#define	ERROR_INVALID_EL1t   3

EL1h
For exceptions taken from EL1 at the time when dedicated stack pointer was allocated for EL1.
#define	SYNC_INVALID_EL1h   4
#define	IRQ_INVALID_EL1h   5
#define	FIQ_INVALID_EL1h   6
#define	ERROR_INVALID_EL1h   7

EL0_64
For exceptions taken from EL0, while executing in 64-bit mode.
#define	SYNC_INVALID_EL0_64   8
#define	IRQ_INVALID_EL0_64   9
#define	FIQ_INVALID_EL0_64   10
#define	ERROR_INVALID_EL0_64   11

EL0_32
For exceptions taken from EL0, while executing in 32-bit mode.
#define	SYNC_INVALID_EL0_32   12
#define	IRQ_INVALID_EL0_32   13
#define	FIQ_INVALID_EL0_32   14
#define	ERROR_INVALID_EL0_32   15

SCTLR_EL1
SCTLR_EL1, System Control Register (EL1) Section D13.2.116 of AArch64-Reference-Manual.
#define	SCTLR_RESERVED   (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
#define	SCTLR_EE_LITTLE_ENDIAN   (0 << 25)
#define	SCTLR_EOE_LITTLE_ENDIAN   (0 << 24)
#define	SCTLR_I_CACHE_DISABLED   (0 << 12)
#define	SCTLR_D_CACHE_DISABLED   (0 << 2)
#define	SCTLR_MMU_DISABLED   (0 << 0)
#define	SCTLR_MMU_ENABLED   (1 << 0)
#define	SCTLR_VALUE_MMU_DISABLED   (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)

HCR_EL2
HCR_EL2, Hypervisor Configuration Register (EL2) Section D13.2.48 of AArch64-Reference-Manual.
#define	HCR_RW   (1 << 31)
#define	HCR_VALUE   HCR_RW

SCR_EL3
SCR_EL3, Secure Configuration Register (EL3) Section G8.2.125 of AArch64-Reference-Manual.
#define	SCR_RESERVED   (3 << 4)
#define	SCR_RW   (1 << 10)
#define	SCR_NS   (1 << 0)
#define	SCR_VALUE   (SCR_RESERVED | SCR_RW | SCR_NS)

SPSR_EL3
SPSR_EL3, Saved Program Status Register (EL3) Section G8.2.128 of AArch64-Reference-Manual.
#define	SPSR_MASK_ALL   (7 << 6)
#define	SPSR_EL1h   (5 << 0)
#define	SPSR_VALUE   (SPSR_MASK_ALL | SPSR_EL1h)

Detailed Description

Exception type values - System Registers - ARMv8-a.

Macro Definition Documentation

ERROR_INVALID_EL0_32

#define ERROR_INVALID_EL0_32   15

System Error on EL0_32.

ERROR_INVALID_EL0_64

#define ERROR_INVALID_EL0_64   11

System Error on EL0_64.

ERROR_INVALID_EL1h

#define ERROR_INVALID_EL1h   7

System Error on EL1h.

ERROR_INVALID_EL1t

#define ERROR_INVALID_EL1t   3

System Error on EL1t.

FIQ_INVALID_EL0_32

#define FIQ_INVALID_EL0_32   14

Fast Interrupt Request exception on EL0_32.

FIQ_INVALID_EL0_64

#define FIQ_INVALID_EL0_64   10

Fast Interrupt Request exception on EL0_64.

FIQ_INVALID_EL1h

#define FIQ_INVALID_EL1h   6

Fast Interrupt Request exception on EL1h.

FIQ_INVALID_EL1t

#define FIQ_INVALID_EL1t   2

Fast Interrupt Request exception on EL1t.

HCR_RW

#define HCR_RW   (1 << 31)

HCR_VALUE

#define HCR_VALUE   HCR_RW

All other HCR options or'ed.

IRQ_INVALID_EL0_32

#define IRQ_INVALID_EL0_32   13

Interrupt Request exception on EL0_32.

IRQ_INVALID_EL0_64

#define IRQ_INVALID_EL0_64   9

Interrupt Request exception on EL0_64.

IRQ_INVALID_EL1h

#define IRQ_INVALID_EL1h   5

Interrupt Request exception on EL1h.

IRQ_INVALID_EL1t

#define IRQ_INVALID_EL1t   1

Interrupt Request exception on EL1t.

S_FRAME_SIZE

#define S_FRAME_SIZE   256

SCR_NS

#define SCR_NS   (1 << 0)

EL0 and EL1 are in Non-secure state, memory accesses, from those exception levels cannot access Secure memory.

SCR_RESERVED

#define SCR_RESERVED   (3 << 4)

SCR_RW

#define SCR_RW   (1 << 10)

Sets execution state at next lower level to be AArch64.

SCR_VALUE

#define SCR_VALUE   (SCR_RESERVED | SCR_RW | SCR_NS)

All other SCR options or'ed.

SCTLR_D_CACHE_DISABLED

#define SCTLR_D_CACHE_DISABLED   (0 << 2)

Disable data cache.

SCTLR_EE_LITTLE_ENDIAN

#define SCTLR_EE_LITTLE_ENDIAN   (0 << 25)

Work only with little-endian format at EL1.

SCTLR_EOE_LITTLE_ENDIAN

#define SCTLR_EOE_LITTLE_ENDIAN   (0 << 24)

Work only with little-endian format at EL0.

SCTLR_I_CACHE_DISABLED

#define SCTLR_I_CACHE_DISABLED   (0 << 12)

Disable instruction cache.

SCTLR_MMU_DISABLED

#define SCTLR_MMU_DISABLED   (0 << 0)

Disable MMU.

SCTLR_MMU_ENABLED

#define SCTLR_MMU_ENABLED   (1 << 0)

SCTLR_MMU_ENABLED

SCTLR_RESERVED

#define SCTLR_RESERVED   (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)

SCTLR_VALUE_MMU_DISABLED

#define SCTLR_VALUE_MMU_DISABLED   (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)

All other SCTLR options or'ed.

SPSR_EL1h

#define SPSR_EL1h   (5 << 0)

EL1h mode: We are using EL1 dedicated stack pointer.

SPSR_MASK_ALL

#define SPSR_MASK_ALL   (7 << 6)

().

SPSR_VALUE

#define SPSR_VALUE   (SPSR_MASK_ALL | SPSR_EL1h)

All other SPSR options or'ed.

SYNC_INVALID_EL0_32

#define SYNC_INVALID_EL0_32   12

Synchronous exception on EL0_32.

SYNC_INVALID_EL0_64

#define SYNC_INVALID_EL0_64   8

Synchronous exception on EL0_64.

SYNC_INVALID_EL1h

#define SYNC_INVALID_EL1h   4

Synchronous exception on EL1h.

SYNC_INVALID_EL1t

#define SYNC_INVALID_EL1t   0

Synchronous exception on EL1t.

Function Documentation

get_el()

int get_el

(

)

Gets the Exception Level of the processor (For ARMv-8).